Microprocessors are highly complex integrated circuits (ICs) developed primarily for performing logic and arithmetic functions at extremely high speeds, as is well-known in the art. Many sorts of microprocessors have been developed for many specialized purposes, but perhaps the most complex of all microprocessors are those produced to serve as Central Processing Units (CPUs) for such as personal computers.
Early CPU microprocessors were essentially high-performance calculators with circuitry for fetching instructions and data from electronic storage, and for outputting results of calculations and the like. However, with increasing demand for performance, CPUs have evolved at the time of this patent application to include on-board temporary memory, known as internal cache or Level 1 cache, for storing data and commands pre-fetched for processing by the CPU. Some CPUs have separate internal cache structures dedicated to data and commands, and in some CPUs data a commands are stored in the same internal cache. In addition to internal cache, many high-performance CPUs now comprise separate instruction units (IUs) designed to be optimally efficient at certain kinds of operations.
The Intel family of i486.TM. microprocessor CPUs is a good example of the highly complex CPUs described above. The various models of CPUs belonging to this product family are described in detail in the product bulletin "Intel 486.TM. Processor Family", Copyright 1994 by Intel Corporation of Santa Clara, Calif. This book can be ordered under Order Number 242202-001 from Intel, and is incorporated in the present patent application by reference.
Partly because of the high order of complexity described for such CPUs, it is vitally important that each and every transistor and connection for every device and circuit be tested and verified. Any failure in the millions of transistors and connections making up a CPU may at some point be catastrophic. Thorough testing of every component is then absolutely critical, and the device level testing that is necessary has become a larger and larger component of the overall cost of producing such CPUs.
As is well-known in the art, microprocessor CPUs, as with other integrated circuits, are produced by alternating additive and subtractive thin-film techniques on substrates of semiconducting material, commonly doped silicon wafers. At the end of the wafer-based processing, individual chips are separated from wafers, typically by techniques of high-precision diamond sawing.
An individual CPU microprocessor, like most other ICs, is a relatively small, usually rectangular chip having in some cases millions of discrete transistors and miles of interconnecting electrically-conductive traces. The traces are ultimately connected to conductive pads around the periphery of usually one side of the chip. These are the contacts from outside the chip to the internal circuitry of the chip.
Typically, individual chips, at this stage called dies, are mounted to die attach pads in lead frames, fine wires are bonded to the conductive pads around the periphery of each die and adjacent electrical leads, and the individual dies are enclosed in a molds and encapsulated, or welded shut into ceramic carriers, as is well-known in the art, with leads protruding, after trimming, for eventual attachment to pads on a printed circuit board (PCB). In the case of a microprocessor CPU, the PCB may be what is termed in the art a motherboard.
CPUs may be tested either before or after incorporation into packages, as described above. The earlier in the manufacturing process that testing can be done, the better, in most cases, because failures can be rejected early, avoiding expensive subsequent manufacturing steps. Techniques are rapidly being developed for handling and testing CPU chips before the packaging stage, which offers considerable savings. Many CPUs, however, are still tested after encapsulation, because alignment and automatic handling is less critical after packaging.
In the testing process, a packaged CPU is mounted to or into a test socket, which provides connection of each lead to circuitry of a specialized printed circuit board, which leads to computerized testing circuitry in a test machine. In the case of pre-package testing, contacts from a testing apparatus are brought to wire bonding pads on individual dies, in some cases before the dies are separated from a silicon wafer on which they are produced. With contact to testing equipment thus made, each input and output to a CPU can be manipulated, and, through predeveloped software, each transistor and connection of a CPU may be exercised and tested.
Testing individual transistors of a CPU microprocessor is not like testing a large number of individual switches, wherein one might simply activate each switch in turn and test the output for voltage. The interconnect traces on a CPU microprocessor or so small (in some cases on the order of one micron in width), and so close together, that making contact to test individual transistors as one would test devices on a printed circuit board is simply not possible. Many traces, in fact, are buried in the topography of the chip.
Different CPUs in the Intel 486.TM. CPU family have different package designs and pinouts. In various models there are, for example, a 168-pin pin grid array (PGA), a 208-lead SQFP Quad Flat Pack, and a 196-lead PQFP Plastic Quad Flat PAck.
The process of thoroughly testing a CPU is a processs conventionally of applying vectors to the pin, pad, or lead array of the CPU, depending on the point in production at which the CPU is tested, and sensing resulting output vectors, a vector being a pattern of logical ones and zeros pertaining to the entire lead or pin array. For a 168-pin PGA, for example, a vector may be a 168-bit pattern. Once a vector is applied a CPU will typically respond with an output vector (bit pattern), which may be compared with a result expected.
In design of a CPU, test vectors are developed for thorough testing. Conventionally a CPU to be tested is mounted or interfaced, as described briefly above, with contact from the pins, pads, or leads to and through a test board to a computerized testing apparatus. The computerized testing apparatus executing specially prepared testing software, rapidly applies test vectors and reads responses sequentially until all of the transistors and connections of the test-object CPU are verified. If, at any point in the testing process responses are inappropriate for a properly operating CPU, the testing apparatus can take appropriate action, depending on the nature of the apparatus. CPUs to be tested, for example, are typically numbered or otherwise identified, so a testing apparatus can list the number of the CPU and associate with that number the point in the test at which failure was encountered.
The testing process, by virtue of the number of individual circuits and transistors in a CPU, can be a long and involved process, requiring duplication of expensive testing equipment to provide a suitable chip testing rate. Moreover, by virtue of the many mounts and contacts that have to be made, false failures may often be encountered. That is, a test meant to verify a particular transistor may indicate a failed transistor by virtue of a poor contact between a lead and a socket pad, or by virtue of a long electrical path with high inductance, even though the CPU is actually not faulty at all.
Inclusion of relatively large amounts of internal cache memory on CPUs has made the testing process even more critical and time consuming. The Intel 486.TM. family, for example, depending on model, has internal cache of either 8 kByte or 16 kByte. As the size of internal cache increases, the number of vectors needed to completely test the memory grows exponentially, consuming correspondingly greater test resources. In the Intel 486.TM. family of CPUs provision is made in some instances to test internal cache memory on-chip. Chapter 11.0 of the handbook referenced above, "Intel 486.TM. Processor Family", is devoted to Built-in self test (BIST). This ability, however, is exclusive, and other testing of chip elements and connections cannot be made while the BIST mode is operating.
To reduce the expense of CPU testing and to simultaneously increase reliability, what is needed is hardware and/or firmware incorporated in the CPU to be tested, together with unique test vectors to be presented by a computerized testing apparatus, whereby the test-object CPU, after conventional testing of a single IU and a portion of internal cache, may be utilized through the tested IU to test the remainder of internal cache in parallel with testing of other IUs. Doing these operation in parallel can reduce overall testing time for some CPUs by half, providing considerable savings in the testing process.